The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight, and high efficiency. For example, SMPSs are widely used in personal computers and portable electronic devices such as cell phones. An SMPS achieves these advantages by switching a switching element such as a power MOSFET at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching defining the efficiency with which an input voltage is converted to a desired output voltage. Switched mode power supplies have for many years been designed for highpower efficiency in the load range of 50 to 100%. This has led to the adoption of techniques such as synchronous rectification, which yield high efficiency at higher current levels.
FIG. 1 shows a background example of a known hard-switched, isolated SMPS, i.e. an SMPS which converts an input voltage Vin to an output voltage Vout whilst isolating the input from the output through an isolation transformer. The SMPS 100 is provided in the form of a full-bridge (DC-to-DC) converter which has on its primary side a primary side drive circuit having transistors Q1, Q2, Q3 and Q4 (which may, for example, be field-effect transistors such as MOSFETs or IGBTs) which are connected between the power supply's inputs and to the primary winding 111 of the isolation transformer 110 in a full-bridge arrangement, as shown. The transistors Q1-Q4 are thus configured to drive the primary winding 111 in response to switching control signals applied thereto.
The switching of the transistors is controlled by a switching control circuit comprising a switch driving circuit 120, a pulse width modulation (PWM) controller, and an error signal generator 140. The driving circuit 120 and PWM controller 130 together function as a switching control signal generator. More specifically, the driving circuit 120 generates respective drive pulses to be applied to the gates of transistors Q1-Q4 in order to turn the transistors ON or OFF, the drive pulses being generated in accordance with switching control signals provided to the drive circuit 120 by the PWM controller 130. In turn, the PWM controller 130 is arranged to receive an error signal generated by the error signal generator 140. The error signal provides a measure of the difference between the output of the SMPS 100 (here, the output voltage Vout) and a reference for the output, which is a reference voltage Vref in the present example. In the present example, the error signal from the error signal generator 140 passes through an electrical isolation barrier 150 (e.g. one or more opto-electric converters) provided between the primary and secondary side circuits of the SMPS 100.
FIG. 1 also shows a standard topology on the secondary side of the isolated SMPS 100, which includes a rectifying circuit and an LC filter connected to a load 160. The inductor 170 of the LC filter is connected to the secondary winding 112 of the transformer 110. A centre-tap (or “mid-tap”) 113 is provided in the secondary winding 112. In the present example, the rectifying network in the secondary side circuit employs two transistors, Q5 and Q6, to yield full-wave rectification of the voltage induced in the secondary winding 112. Each of the switching devices Q5 and Q6 can take any suitable or desirable form, and are preferably field-effect transistors in the form of a MOSFET or an IGBT, for example. The switching of these transistors is controlled by the same switching control signal generator that controls the switching of transistors Q1-Q4, namely that comprising the drive circuit 120 and the PWM controller 130. The portion of the SMPS 100 circuit identified at 180 in FIG. 1 constitutes the so-called “power train” of the SMPS 100.
As with most SMPS topologies, the output voltage Vout in this example is proportional to the input voltage Vin. More specifically, Vout∝nDVin, where D is the switching duty cycle ratio and n is the transformer turns ratio.
The timings according to which the transistors Q1-Q6 of the SMPS 100 of FIG. 1 are switched are illustrated by timing diagrams A-D of FIG. 2 for the case where the SMPS 100 operates with a relatively large duty cycle of about 85%. Switching the transistors Q1-Q6 in accordance with timing diagrams A-D causes the SMPS 100 to operate in the well-known “Continuous Conduction Mode” (CCM), with the current IL through the inductor 170 oscillating in the manner shown in trace E of FIG. 2 while remaining greater than zero throughout each switching period Ts. As can be appreciated from timing diagrams C and D, when the SMPS 100 operates in CCM, at least one of the transistors in the secondary side circuit is configured to be in a conductive state (i.e. turned ON) at any given point in time. In other words, during operation in CCM, at no stage of the SMPS switching cycle is the conduction path for the inductor current IL blocked by all of the transistors in the secondary side circuit.
The amplitude of the oscillation in the inductor current, Iripple/2 (shown in trace E of FIG. 2) is a function of the input voltage Vin to the SMPS 100, the switching duty cycle D, the switching period Ts employed by the switching controller 130, and the inductance L of the inductor 170. Accordingly, when the SMPS 100 is operated with a lower duty cycle, as illustrated by timing diagrams A-D of FIG. 3, the amplitude of the ripple current is reduced, as shown in trace E of FIG. 3.
However, the size of the ripple current is not dependent on the SMPS load resistance R and will therefore not change when the load resistance R increases and the output current Iout of the SMPS consequently decreases. Thus, when the value of R increases while the remaining operational parameters of the SMPS 100 (such as D and Ts) stay unchanged, the dc component, ILdc, of the inductor current IL will eventually decrease to below Iripple/2, and the inductor current IL will become negative during a portion of each switching period, as illustrated in trace F of FIG. 3.
At such low output current levels, an SMPS employing synchronous rectification on the secondary side in accordance with the switching scheme shown in FIG. 3 will usually be less efficient than a similar SMPS that employs diode rectification on the secondary side. In order to improve the light load efficiency, it is therefore known to use diode emulation to cause the synchronous secondary side circuit to mimic diode rectification. In this case, transistors Q5 and Q6 are controlled to behave like current-unidirectional switches (such as diodes) that conduct current only when the inductor current IL is above a threshold.
Examples of switch timing diagrams which may be used to emulate diode rectification on the secondary side of the SMPS 100 are shown in FIG. 4. Although the timing diagrams for transistors pairs Q1/Q4 and Q2/Q3 on the primary side are the same as those in diagrams A and B in FIG. 3, the timings for the secondary side transistors Q5 and Q6 are adjusted such that the inductor current IL is not allowed to fall below zero at any stage of the switching cycle. In this way, transistors Q5 and Q6 are controlled to behave like diodes, which become reverse biased and thus block current flow when the inductor current IL falls to zero. The inductor current IL is thus held at zero for a portion of each switching cycle, as shown in trace E of FIG. 4, and the SMPS 100 operates in the well-known “Discontinuous Conduction Mode” (DCM). In the DCM, while the inductor current IL is zero, energy is supplied to the SMPS load circuit by the filter capacitor 190. However, diode emulation leads to certain problems with the compensator design, which will now be discussed.
When operating an SMPS in a diode emulation mode, the current in the inductor 170 becomes discontinuous when the dc component of the inductor current falls below Iripple/2. This makes the duty cycle D dependent on the current, as explained insection 5.1 in Chapter 5 of “Fundamentals of Power Electronics” by R. W. Erickson and D. Maksimović (Second Edition, ISBN: 0-7923-7270-0). In brief, it can be shown from a consideration of the inductor volt-second balance and capacitor charge balance that the output voltage Vout of the SMPS 100 takes the following forms in CCM and DCM:
                              V          out                =                  {                                                                      nDV                  in                                                                              K                  >                                                            K                      crit                                        ⁢                                                                                  ⁢                                          i                      .                      e                      .                                                                                          ⁢                      CCM                                                                                                                                                                2                    ⁢                                                                                  ⁢                                          nV                      in                                                                            1                    +                                                                  1                        +                                                  4                          ⁢                                                                                                          ⁢                                                      K                            /                                                          D                              2                                                                                                                                                                                                                        K                  <                                                            K                      crit                                        ⁢                                                                                  ⁢                                          i                      .                      e                      .                                                                                          ⁢                      DCM                                                                                                                              Equation        ⁢                                  ⁢        1            
In Eqn. 1, the dimensionless parameter K=2L/RTs and Kcrit=1−D. In order to keep the output voltage Vout constant in DCM, the factor K/D2 must be held constant. Solving for the duty cycle we obtain:
                    D        ∝                  1                      R                          ∝                              I            0                                              Equation        ⁢                                  ⁢        2            
Hence, with decreasing load current, i.e. increasing value of R, the duty cycle D is required to decrease. This means that the duty cycle D has to change by a large amount when SMPS operation changes between CCM and DCM. In other words, the gain in the system varies strongly with the load current and this requires substantial changes to the duty cycle D to be made as the load current changes.
In conventional SMPS controllers, a gain scheduling approach is usually adopted and different compensators are provided for the different working regions, which increases the complexity of the controller. Moreover, as will be demonstrated by way of experimental results in the following, the large changes to the duty cycle D that are required as the SMPS 100 transitions between operating in CCM and DCM cause large transients to appear in the output voltage of the SMPS 100. It is therefore highly desirable to maximise light load efficiency of an SMPS whilst improving its output transient performance.